Altera Arria II GX FPGA Development Board - Manual (Page 63)

February 2011 Altera Corporation Arria II GX FPGA Development Board Reference Manual
Additional Information
This chapter provides additional information about the document and Altera.
Document Revision History
The following table shows the revision history for this document.
How to Contact Altera
To locate the most up-to-date information about Altera products, refer to the
following table.
Date Version Changes
February 2011 1.2
■ Updated LCD PWRMON (board settings DIP switch) description in Table 2–13 .
■ Updated “DDR3” and “DDR2 SODIMM” sections to reflect the interface modification in
the new board version (production silicon speed grade C4N device).
■ Updated the manufacturing part number of the flash device in Table 2–47 .
■ Updated the PFL Megafunction and memory interface document reference links.
■ Converted document to new frame template and made textual and style changes.
October 2009 1.1
■ Corrected pin assignments in Table 2–7 , Table 2–23 , Table 2–34 , Table 2–35 , Table 2–37 ,
Table 2–38 , Table 2–40 , Table 2–42 , Table 2–44 , Table 2–46 .
■ Corrected schematic signal names in Table 2–17 .
■ Corrected munufacturing information in Table 2–19 and Table 2–24 .
July 2009 1.0 Initial release.
Contact (1) Contact Method Address
Technical support Website www.altera.com/support
Technical training
Website www.altera.com/training
Email [email protected]
Product literature Website www.altera.com/literature
Non-technical support (General) Email [email protected]
(Software Licensing) Email [email protected]
Note to Table:
(1) You can also contact your local Altera sales office or sales representative.