Altera Arria II GX FPGA Development Board - Manual (Page 17)

Chapter 2: Board Components 2–9
MAX II CPLD EPM2210 System Controller
February 2011 Altera Corporation Arria II GX FPGA Development Board Reference Manual
flash_wen
2.5-V
D7 C7 FSM bus flash memory write enable
fpga_conf_done J1 AE25 FPGA configuration done
fpga_config_d[0] B1 N26 FPGA configuration data
fpga_config_d[1] A4 N6 FPGA configuration data
fpga_config_d[2] A7 G2 FPGA configuration data
fpga_config_d[3] B4 P6 FPGA configuration data
fpga_config_d[4] B5 L4 FPGA configuration data
fpga_config_d[5] A6 K3 FPGA configuration data
fpga_config_d[6] A5 M4 FPGA configuration data
fpga_config_d[7] B6 K2 FPGA configuration data
fpga_dclk H4 L25 FPGA configuration clock
fpga_nconfig J2 AC26 FPGA configuration active
fpga_nstatus H3 AD28 FPGA configuration ready
fsm_a[0] A2 M21 FSM bus address
fsm_a[1] D9 J3 FSM bus address
fsm_a[10] B16 C24 FSM bus address
fsm_a[11] C15 E25 FSM bus address
fsm_a[12] D16 F21 FSM bus address
fsm_a[13] D10 J19 FSM bus address
fsm_a[14] A15 H19 FSM bus address
fsm_a[15] C11 K21 FSM bus address
fsm_a[16] A12 L21 FSM bus address
fsm_a[17] B12 F25 FSM bus address
fsm_a[18] C12 F26 FSM bus address
fsm_a[19] B13 G23 FSM bus address
fsm_a[2] E10 D29 FSM bus address
fsm_a[20] A13 H21 FSM bus address
fsm_a[21] B14 M13 FSM bus address
fsm_a[22] D11 P7 FSM bus address
fsm_a[23] E9 F10 FSM bus address
fsm_a[24] D6 R4 FSM bus address
fsm_a[25] C13 K4 FSM bus address
fsm_a[3] E4 J21 FSM bus address
fsm_a[4] E5 L13 FSM bus address
fsm_a[5] E14 C8 FSM bus address
fsm_a[6] G15 N9 FSM bus address
fsm_a[7] E15 D20 FSM bus address
fsm_a[8] F16 A23 FSM bus address
fsm_a[9] E16 B24 FSM bus address
Table 2–7. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 3 of 5)
Schematic Signal Name I/O Standard
EPM2210
Pin Number
EP2AGX125
Pin Number
Description