Search
beautypg.com
Directory
Brands
Altera manuals
Measuring instruments
Viterbi Compiler
Manual
Altera Viterbi Compiler User Manual
Viterbi ip core user guide
Text mode
Original mode
Altera Viterbi Compiler User Manual | 40 pages
Pages:
1
2
3
4
5
6
7
…
40
wrong Brand
wrong Model
non readable
Table of contents
Document Outline
Viterbi IP Core User Guide
Contents
1. About the Viterbi IP Core
Altera DSP IP Core Features
Viterbi II IP Core Features
DSP IP Core Device Family Support
DSP IP Core Verification
Viterbi IP Core Release Information
Viterbi IP Core Performance and Resource Utilization
2. Viterbi IP Core Getting Started
Installing and Licensing IP Cores
OpenCore Plus IP Evaluation
Viterbi IP Core OpenCore Plus Timeout Behavior
IP Catalog and Parameter Editor
Specifying IP Core Parameters and Options
Files Generated for Altera IP Cores
Simulating Altera IP Cores in other EDA Tools
DSP Builder Design Flow
3. Viterbi IP Core Functional Description
Decoder
Convolutional Encoder
Trellis Coded Modulation
Half-Rate Convolutional Codes
Trellis Decoder
About Converting Received Signals
Trellis Termination
Trellis Initialization
Viterbi IP Core Parameters
Architecture
BER Estimator
Node Synchronization
Code Sets
Viterbi Parameters
Soft Symbol Input
State Metrics
Throughput Calculator
Latency Calculator
Test Data
External Puncturing
Viterbi IP Core Interfaces and Signals
Avalon-ST Interfaces in DSP IP Cores
Global Signals
Avalon-ST Sink Signals
Avalon Source-ST Signals
Configuration Signals
Status Signals
Viterbi IP Core Timing Diagrams
4. Document Revision History
See also other documents in the category Altera Measuring instruments:
MAX 10 JTAG
(15 pages)
MAX 10 Power
(21 pages)
Unique Chip ID
(12 pages)
Remote Update IP Core
(43 pages)
Device-Specific Power Delivery Network
(28 pages)
Device-Specific Power Delivery Network
(32 pages)
Hybrid Memory Cube Controller
(69 pages)
ALTDQ_DQS IP
(117 pages)
MAX 10 Embedded Memory
(71 pages)
MAX 10 Embedded Multipliers
(37 pages)
MAX 10 Clocking and PLL
(86 pages)
MAX 10 FPGA
(26 pages)
MAX 10 FPGA
(56 pages)
USB-Blaster II
(22 pages)
GPIO
(22 pages)
LVDS SERDES
(27 pages)
User Flash Memory
(33 pages)
ALTDQ_DQS2
(100 pages)
Avalon Tri-State Conduit Components
(18 pages)
Cyclone V Avalon-MM
(166 pages)
Cyclone III FPGA Starter Kit
(36 pages)
Cyclone V Avalon-ST
(248 pages)
Stratix V Avalon-ST
(286 pages)
Stratix V Avalon-ST
(293 pages)
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP
(10 pages)
Arria 10 Avalon-ST
(275 pages)
Avalon Verification IP Suite
(224 pages)
Avalon Verification IP Suite
(178 pages)
FFT MegaCore Function
(50 pages)
DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP
(140 pages)
Floating-Point
(157 pages)
Integer Arithmetic IP
(157 pages)
Embedded Peripherals IP
(336 pages)
JESD204B IP
(158 pages)
Low Latency Ethernet 10G MAC
(109 pages)
LVDS SERDES Transmitter / Receiver
(72 pages)
Nios II Embedded Evaluation Kit Cyclone III Edition
(3 pages)
Nios II Embedded Evaluation Kit Cyclone III Edition
(80 pages)
IP Compiler for PCI Express
(372 pages)
Parallel Flash Loader IP
(57 pages)
Nios II C2H Compiler
(138 pages)
RAM-Based Shift Register
(26 pages)
RAM Initializer
(36 pages)
Phase-Locked Loop Reconfiguration IP Core
(51 pages)
DCFIFO
(28 pages)
