Altera Viterbi Compiler - Manual (Page 30)

Soft Symbol Meaning
100 Strongest '1'
State Metrics
The Viterbi decoder state metrics are accumulative not Euclidean and are based on maximum metrics
rather than minimum metrics.
As the metrics grow, normalize them to avoid overflow. When a normalization occurs the decoder
subtracts 2 (bmgwide – 1) from all metrics and increases the normalization register by +1. The total metric
value for the best path = (number of normalizations) × (2 (bmgwide – 1) ) + bestmet. The total metric value for
the best path, the number of symbols processed, and the number of errors in the BER block indicate the
quality of the channel and whether you have a suitable value for softbits. The output bestadd indicates the
state that has the best metric.
Throughput Calculator
The throughput calculator uses the following equation:
Hybrid throughput = f
MAX
/Z
where:
• • Z = 10, if log2C = 3
• Z= 2log2C, if log2C > 3
• log2C = L
MAX
– 2 – log2A
• L
MAX
is the maximum constraint length
• A is ACS units
• Parallel throughput = f
MAX
Latency Calculator
The latency calculator gives you an approximate indication of the latency of your Viterbi decoder.
Latency is the number of clock cycles it takes the decoder to process r the data and output it. Latency is
from the first symbol to enter the IP core (
sink_sop
) up to the first symbol to leave (
source_sop
). The
latency depends on the parameters. For the precise latency, perform simulation. The latency calculator
uses the following formula for the hybrid architecture:
Number of clock cycles = Z × V
where:
• • V is the traceback length value that is in the input
tb_length
• Z = 10, if log2C = 3
• Z = 2log2C, if log2C > 3
• log2C = L
MAX
– 2 – log2A, where A is ACS units
For the parallel architecture the number of clock cycles is approximately 4V.
Test Data
3-12 State Metrics
UG-VITERBI
2014.12.15
Altera Corporation Viterbi IP Core Functional Description
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