Altera Viterbi Compiler - Manual (Page 16)

File Name Description
<my_ip>.svd Allows HPS System Debug tools to view the register maps of
peripherals connected to HPS within a Qsys system.
During synthesis, the .svd files for slave interfaces visible to System
Console masters are stored in the .sof file in the debug section.
System Console reads this section, which Qsys can query for register
map information. For system slaves, Qsys can access the registers by
name.
<my_ip>.v
or
<my_ip>.vhd
HDL files that instantiate each submodule or child IP core for
synthesis or simulation.
mentor/ Contains a ModelSim ® script msim_setup.tcl to set up and run a
simulation.
aldec/ Contains a Riviera-PRO script rivierapro_setup.tcl to setup and run a
simulation.
/synopsys/vcs
/synopsys/vcsmx
Contains a shell script vcs_setup.sh to set up and run a VCS ®
simulation.
Contains a shell script
vcsmx_setup.sh and synopsys_ sim.setup file to
set up and run a VCS MX ® simulation.
/cadence Contains a shell script ncsim_setup.sh and other setup files to set up
and run an NCSIM simulation.
/submodules Contains HDL files for the IP core submodule.
<child IP cores>/ For each generated child IP core directory, Qsys generates /synth and /
sim sub-directories.
Simulating Altera IP Cores in other EDA Tools
The Quartus II software supports RTL and gate-level design simulation of Altera IP cores in supported
EDA simulators. Simulation involves setting up your simulator working environment, compiling
simulation model libraries, and running your simulation.
You can use the functional simulation model and the testbench or example design generated with your IP
core for simulation. The functional simulation model and testbench files are generated in a project
subdirectory. This directory may also include scripts to compile and run the testbench. For a complete list
of models or libraries required to simulate your IP core, refer to the scripts generated with the testbench.
You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts.
NativeLink launches your preferred simulator from within the Quartus II software.
UG-VITERBI
2014.12.15
Simulating Altera IP Cores in other EDA Tools 2-7
Viterbi IP Core Getting Started Altera Corporation
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