Altera Viterbi Compiler - Manual (Page 2)

Contents
About the Viterbi IP Core...................................................................................1-1
Altera DSP IP Core Features...................................................................................................................... 1-1
Viterbi II IP Core Features......................................................................................................................... 1-1
DSP IP Core Device Family Support.........................................................................................................1-2
DSP IP Core Verification............................................................................................................................1-2
Viterbi IP Core Release Information.........................................................................................................1-2
Viterbi IP Core Performance and Resource Utilization.........................................................................1-3
Viterbi IP Core Getting Started.......................................................................... 2-1
Installing and Licensing IP Cores..............................................................................................................2-1
OpenCore Plus IP Evaluation........................................................................................................ 2-1
Viterbi IP Core OpenCore Plus Timeout Behavior.................................................................... 2-2
IP Catalog and Parameter Editor...............................................................................................................2-2
Specifying IP Core Parameters and Options............................................................................................2-3
Files Generated for Altera IP Cores...............................................................................................2-4
Simulating Altera IP Cores in other EDA Tools..................................................................................... 2-7
DSP Builder Design Flow............................................................................................................................2-8
Viterbi IP Core Functional Description............................................................. 3-1
Decoder......................................................................................................................................................... 3-1
Convolutional Encoder............................................................................................................................... 3-1
Trellis Coded Modulation...........................................................................................................................3-2
Half-Rate Convolutional Codes.....................................................................................................3-2
Trellis Decoder................................................................................................................................. 3-4
About Converting Received Signals.............................................................................................. 3-5
Trellis Termination..........................................................................................................................3-7
Trellis Initialization .........................................................................................................................3-7
Viterbi IP Core Parameters........................................................................................................................ 3-7
Architecture...................................................................................................................................... 3-7
Code Sets........................................................................................................................................... 3-9
Viterbi Parameters.........................................................................................................................3-10
Test Data......................................................................................................................................... 3-12
Viterbi IP Core Interfaces and Signals....................................................................................................3-14
Avalon-ST Interfaces in DSP IP Cores....................................................................................... 3-14
Global Signals................................................................................................................................. 3-14
Avalon-ST Sink Signals.................................................................................................................3-14
Avalon Source-ST Signals.............................................................................................................3-16
Configuration Signals....................................................................................................................3-17
Status Signals.................................................................................................................................. 3-18
Viterbi IP Core Timing Diagrams...............................................................................................3-18
TOC-2
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