Altera Viterbi Compiler User Manual
Page 24
![background image](https://www.manualsdir.com/files/763787/content/doc024.png)
Figure 3-6: Conversion of Received Symbol into Four Branch Metrics and a Sector Number
Branch Metric 1
Branch Metric 3
Branch Metric 2
Branch Metric 0
Received Symbol
011
001
000
110
111
101
100
010
2
For example, consider a received symbol that lands in sector number 2 with the following distances to the
four nearest symbol map points:
• 1111
• 1101
• 1011
• 0001
Where the distance of the radius for 4 softbits is 1111. The distances are inverted to obtain the following
branch metrics:
• Branch metric 0 = 0000
• Branch metric 1 = 0010
• Branch metric 2 = 0100
• Branch metric 3 = 1110
The decoder uses the coded bits (c1, c0) to select the branch metric number, which it uses to decide where
to connect the branch metrics to the rr input of the Viterbi decoder. Branch metric 3 goes to the most
significant bits (MSB) of
rr
; branch metric 0 goes to the least significant bits (LSB) of
rr
.
3-6
About Converting Received Signals
UG-VITERBI
2014.12.15
Altera Corporation
Viterbi IP Core Functional Description
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)