Altera Viterbi Compiler - Manual (Page 37)

Figure 3-10: Hybrid Decoder Input Timing Diagram
The
sink_rdy
signal is asserted for one clock cycle in every Z clock cycles. If the decoder becomes full
because data is not being collected on the source side, it may deassert
sink_rdy
until it can accept new
data. The decoder only accepts data, if
sink_rdy
is asserted.
clk
sink_rdy
sink_val
sink_sop
sink_eop
rr[8:1] 77 88 88
Figure 3-11: Parallel Decoder Input Timing Diagram
clk
sink_rdy
sink_val
sink_sop
sink_eop
rr[8:1] valid data valid data
Figure 3-12: Output Timing - Example 1
The
source_val
signal is asserted initially for 8 or 16 clock cycles. It is then asserted for the number of
clock cycles corresponding to the amount of remaining data, if
source_rdy
remains asserted. The typical
ending of a block or packet in the Avalon-ST interface is on the source (Viterbi) to the sink (user) side
connection.
clk
source_sop
source_eop
source_rdy
source_val
decbit
UG-VITERBI
2014.12.15
Viterbi IP Core Timing Diagrams 3-19
Viterbi IP Core Functional Description Altera Corporation
Send Feedback