Status, Status –8 – Altera Stratix V Advanced Systems User Manual
Page 26

5–8
Chapter 5: Board Test System
Using the Board Test System
Stratix V Advanced Systems Development Kit
February 2013
Altera Corporation
User Guide
shows the FMC/C2C tab.
1
For factory testing, you must have an FMC loopback card installed on the FMC
connector (J8) for this test to work correctly. Altera recommends the Acquitek FMC
Loopback Test Mezzanine (part number AF101). Otherwise, set the PMA setting tab to
test internal loopback mode (serial loopback = 1).
The following sections describe the controls on the FMC/C2C tab.
Status
The Status control displays the following status information during the loopback test:
■
PLL lock
—Shows the PLL locked or unlocked state.
■
Channel lock
—Shows the channel locked or unlocked state. When locked, all
lanes are word aligned and channel bonded.
■
Pattern sync
—Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected.
Figure 5–5. The FMC/C2C Tab
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)