Altera Stratix V Advanced Systems - Manual (Page 13)

February 2013 Altera Corporation Stratix V Advanced Systems Development Kit
User Guide
4. Development Board Setup
The instructions in this chapter explain how to set up the Stratix V GX advanced
systems board.
Setting Up the Board
To prepare and apply power to the board, perform the following steps:
1. The Stratix V GX advanced systems board ships with its board switches
preconfigured to support the design examples in the kit. If you suspect your board
might not be currently configured with the default settings, follow the instructions
in
“Factory Default Switch and Jumper Settings” on page 4–2 to return the board
to its factory settings before proceeding.
2. The advanced systems board ships with design examples stored in the flash
memory device. Verify the DIP switch SW4.6 is set to the on (0) position to load the
design stored in the factory portion of flash memory.
Figure 4–2 shows the DIP
switch location on the back of the board.
3. Verify that the HSMC card is installed on connector J1 of the board.
4. Ensure that the power switch SW2 is in the off position.
5. Connect the Power Adpater +15 V, 8.00 A to the DC Power Jack (J7) on the
advanced systems board and plug the cord into a power outlet.
c Use only the supplied power supply. Power regulation circuitry on the
board can be damaged by power supplies with greater voltage.
1 For designs requiring more than 120 W, a PCIe 2x4 ATX connector (J10)
providing an additional 12 V and 12.5 A is also available. This is the
standard PCIe 2x4 connector in a chassis or available with an ATX power
supply.
1
Alternatively, the board can be powered by the PCIe host adapter or the
laptop power adapter. If you want to power the board by the PCIe host
system, plug the FPGA development card into a standard PCIe connector.
6. Set the POWER switch (SW2) to the on position. When power is supplied to the
board, the blue LED (D27) illuminates indicating that the board has power.
The MAX V device on the board contains (among other things) a parallel flash loader
(PFL) megafunction. When the board powers up, the PFL reads a design from flash
memory and configures the FPGA. DIP switch SW4.6 controls whether the FPP is
active and loads the designs from flash into the Stratix V devices. When the switch is
in the on (0) position, the PFL loads the design from flash memory. For FPP to
function properly, the MSEL pins for both FPGAs must be set for FPP x8 on MSEL DIP
switches SW5 and SW6.