Altera Stratix V Advanced Systems User Manual
Page 16
4–4
Chapter 4: Development Board Setup
Factory Default Switch and Jumper Settings
Stratix V Advanced Systems Development Kit
February 2013
Altera Corporation
User Guide
2. Set DIP switch (SW5) to match
3. Set DIP switch (SW6) to match
4. Set DIP switch (SW7) to match
Table 4–2. SW5 FPGA1 MSEL DIP Switch Settings
Switch
Board Label
Function
Default
Position
1
FPGA1 MSEL0
FPGA1 MSEL bit 0 configuration setting
On (0)
2
FPGA1 MSEL1
FPGA1 MSEL bit 1 configuration setting
On (0)
3
FPGA1 MSEL2
FPGA1 MSEL bit 2 configuration setting
Off (1)
4
—
—
—
Notes to
(1) FPGA1 MSEL[4:3]=10 is hard wired on the board.
(2) FPGA1 MSEL[4:0] to valid configuration schemes as listed in the Stratix V Device Handbook.
(3) By default, FPGA1 MSEL is set for FPP x8.
Table 4–3. SW6 FPGA2 MSEL DIP Switch Settings
Switch
Board Label
Function
Default
Position
1
FPGA2 MSEL0
FPGA2 MSEL bit 0 configuration setting
On (0)
2
FPGA2 MSEL1
FPGA2 MSEL bit 1 configuration setting
On (0)
3
FPGA2 MSEL2
FPGA2 MSEL bit 2 configuration setting
Off (1)
4
—
—
—
Notes to
(1) FPGA2 MSEL[4:3]=10 is hard wired on the board.
(2) FPGA2 MSEL[4:0] to valid configuration schemes as listed in the Stratix V Device Handbook.
(3) By default, FPGA2 MSEL is set for FPP x8.
Table 4–4. SW7 JTAG DIP Switch Settings
Switch
Board Label
Function
Default
Position
1
HSMC
Switch 1 has the following options:
■
When on (1), removes the HSMC from the JTAG
chain.
■
When off (0), includes the HSMC in the JTAG
chain.
On (1)
2
FMC
Switch 1 has the following options:
■
When on (1), removes the FMC from the JTAG
chain.
■
When off (0), includes the FMC in the JTAG chain.
On (1)
3
—
—
—
4
—
—
—
Note to
:
(1) If you plug in an external USB-Blaster cable to the JTAG header (J11), the On Board USB-Blaster II is disabled. The
JTAG chain is normally mastered by the On-board USB-Blaster II.