Push button switches, The gpio fpga2 tab, User dip switches – Altera Stratix V Advanced Systems User Manual
Page 24: Push button switches –6, The gpio fpga2 tab –6, User dip switches –6

5–6
Chapter 5: Board Test System
Using the Board Test System
Stratix V Advanced Systems Development Kit
February 2013
Altera Corporation
User Guide
Push Button Switches
The read-only Push button switches control displays the current state of the board
user push buttons. Press a push button on the board to see the graphical display
change accordingly.
The GPIO FPGA2 Tab
The GPIO FPGA2 tab allows you to interact with all the general purpose user I/O
components on your board associated with FPGA2 (U35). You can read DIP switch
settings, turn LEDs on or off, and detect push button presses. This test erases FPGA1.
shows the GPIO FPGA2 tab.
The following sections describe the controls on the GPIO FPGA2 tab.
User DIP Switches
The read-only User DIP switch control displays the current positions of the switches
in the user DIP switch bank (SW3). Change the switches on the board to see the
graphical display change accordingly.
Figure 5–4. The GPIO FPGA2 Tab
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)