Altera Stratix V Advanced Systems - Manual (Page 22)

5–4 Chapter 5: Board Test System
Using the Board Test System
Stratix V Advanced Systems Development Kit February 2013 Altera Corporation
User Guide
The System Info Tab
The System Info tab shows information about the board’s current configuration.
Figure 5–1 on page 5–1 shows the System Info tab. The tab displays the contents of
the MAX V registers, the JTAG chain, the flash memory map, and other details stored
on the board.
The following sections describe the controls on the System Info tab.
Board Information
The Board information control displays static information about your board.
■ Board Name —Indicates the official name of the board.
■ Board P/N —Indicates the part number of the board.
■ Serial number —Indicates the serial number of the board.
■ Factory test version —Indicates the version of the Board Test System currently
running on the board.
JTAG Chain
The JTAG chain control shows all the devices currently in the JTAG chain. The
Stratix V GX devices are always the first devices in the chain, and the MAX V is
always the last device in the chain. The JTAG chain is normally mastered by the
On-board USB-Blaster II.
1 If you plug in an external USB-Blaster cable to the JTAG header (J11), the On-Board
USB-Blaster II is disabled.
1 DIP switch SW7 selects which interfaces are in the chain. Set SW7 switch positions in
the off position to include the interface in the JTAG chain. Refer to
Table 4–4 on
page 4–4 for detailed settings.
f For details on the JTAG chain, refer to the Stratix VAdvanced Systems Development
Board Reference Manual. For USB-Blaster II configuration details, refer to the On-Board
USB-Blaster II page.