Factory default switch and jumper settings, Factory default switch and jumper settings –2 – Altera Stratix V Advanced Systems User Manual
Page 14
4–2
Chapter 4: Development Board Setup
Factory Default Switch and Jumper Settings
Stratix V Advanced Systems Development Kit
February 2013
Altera Corporation
User Guide
1
The kit includes a MAX V design which contains the MAX V PFL megafunction. The
design resides in the
directory.
When configuration is complete, the Config Done LED (D13) illuminates, signaling
that the Stratix V GX devices configured successfully.
f
For more information about the PFL megafunction, refer to
Factory Default Switch and Jumper Settings
This section shows the factory switch and jumper settings for the Stratix V GX
advanced systems board.
shows the switch locations and the default position of each switch and
jumper on the top side of the board.
Figure 4–1. Default Settings
on the Board Top (Detail)
J3
VCCIO_FMC
1.8 V
1.5 V
1.2 V
Default:
no jumper installed
for 2.5 V
SW1
7
0
1
6543210
ON
J2
FA
N1
SW3
7
0
1
6543210
ON
J12
FAN2
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)