Altera Stratix IV E FPGA - Manual (Page 48)

6–22 Chapter 6: Board Test System
The Power Monitor
Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation
The Power Monitor communicates with the MAX II device on the board through the
JTAG bus. A power monitor circuit attached to the MAX II device allows you to
measure the power that the Stratix IV E FPGA device is consuming regardless of the
design currently running.
Figure 6–10 shows the Power Monitor.
The following sections describe the Power Monitor controls.
General Information
The General information controls display the following information about the
MAX II device:
■ MAX II version —Indicates the version of MAX II code currently running on the
board. The MAX II code resides in the dir>\kits\stratixIVE_4se530_fpga\factory_recovery and dir>\kits\stratixIVE_4se530_fpga\examples\max2 directories. Newer revisions
of this code might be available on the
Stratix IV E FPGA Development Kit page of
the Altera website.
Figure 6–10. The Power Monitor