Altera Stratix IV E FPGA - Manual (Page 47)

Chapter 6: Board Test System 6–21
The Power Monitor
June 2011 Altera Corporation Stratix IV E FPGA Development Kit User Guide
■ Tx (MBps) and Rx (MBps)—Show the number of bytes of data analyzed per
second. The HSMC x17 SERDES buses on both HSMC A and HSMC B are 17 bits
wide and clocked using the 125 MHz oscillator with a PLL multiplier of 13,
equating to a 1.625 Gbps per pin, or a 27.625 Gbps bandwidth for each x17
SERDES port. The x3 single-ended data bus is 3 bits wide and clocked using a
100 MHz clock single-data-rate for 100 Mbps per pin, or a 300 Mbps bandwidth
for each x3 single-ended data port.
The Power Monitor
The Power Monitor measures and reports current power and temperature
information for the board. To start the application, click Power Monitor in the Board
Test System application.
1
You can also run the Power Monitor as a stand-alone application. PowerTool.exe
resides in the dir>\kits\stratixIVE_4se530_fpga\examples\board_test_system directory. On
Windows, click Start > All Programs > Altera > Stratix IV E FPGA Development Kit
<version> > Power Monitor to start the application.