Altera Stratix IV E FPGA - Manual (Page 42)

6–16 Chapter 6: Board Test System
Using the Board Test System
Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation
■ Write and Read performance bars—Show the percentage of maximum theoretical
data rate that the requested transactions are able to achieve.
■ Write (MBps) and Read (MBps)—Show the number of bytes of data analyzed per
second. The QDR II+ bus is 18 bits wide for both read and write, and the frequency
is 400 MHz double data rate (800 Mbps per pin), equating to a theoretical
maximum bandwidth of 1800 MBps, and 3600 MBps for simultaneous read and
write.
Error Control
The Error control controls display data errors detected during analysis and allow you
to insert errors:
■ Detected errors —Displays the number of data errors detected in the hardware.
■ Inserted errors —Displays the number of errors inserted into the transaction
stream.
■ Insert Error —Inserts a one-word error into the transaction stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
■ Clear —Resets the Detected errors and Inserted errors counters to zeros.
Number of Addresses to Write and Read
The Number of addresses to write and read control determines the number of
addresses to use in each iteration of reads and writes. Valid values range from 8 to
1,048,576.
Data Type
The Data type control specifies the type of data contained in the transactions. The
following data types are available for analysis:
■ PRBS —Selects pseudo-random bit sequences.
■ Memory —Selects a generic data pattern stored in the on chip memory of the
Stratix IV E device.
■ Math —Selects data generated from a simple math function within the FPGA
fabric.