Altera Stratix IV E FPGA - Manual (Page 40)

6–14 Chapter 6: Board Test System
Using the Board Test System
Stratix IV E FPGA Development Kit User Guide June 2011 Altera Corporation
■ Write , Read, and Total performance bars—Show the percentage of maximum
theoretical data rate that the requested transactions are able to achieve.
■ Write (MBps) , Read (MBps), and Total (MBps)—Show the number of bytes of
data analyzed per second. The data bus is 72 bits wide and the frequency is
533 MHz double data rate (1066 Mbps per pin), equating to a theoretical
maximum bandwidth of 9594 MBps.
Error Control
The Error control controls display data errors detected during analysis and allow you
to insert errors:
■ Detected errors —Displays the number of data errors detected in the hardware.
■ Inserted errors —Displays the number of errors inserted into the transaction
stream.
■ Insert Error —Inserts a one-word error into the transaction stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
■ Clear —Resets the Detected errors and Inserted errors counters to zeros.
Number of Addresses to Write and Read
The Number of addresses to write and read control determines the number of
addresses to use in each iteration of reads and writes. Valid values range from 8 to
16,777,216.
Data Type
The Data type control specifies the type of data contained in the transactions. The
following data types are available for analysis:
■ PRBS —Selects pseudo-random bit sequences.
■ Memory —Selects a generic data pattern stored in the on chip memory of the
Stratix IV E device.
■ Math —Selects data generated from a simple math function within the FPGA
fabric.
Read and Write Control
The Read and write control specifies the type of transactions to analyze. The
following transaction types are available for analysis:
■ Write then read —Selects read and write transactions for analysis.
■ Read only —Selects read transactions for analysis.
■ Write only —Selects write transactions for analysis.