Jtag chain –6 sopc builder memory map –6, Jtag chain – Altera Stratix IV E FPGA User Manual

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Chapter 6: Board Test System

Using the Board Test System

Stratix IV E FPGA Development Kit User Guide

June 2011

Altera Corporation

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SRST

—Resets the system and reloads the FPGA with a design from flash memory

based on the other MAX II register values. Refer to

Table 6–1

for more information.

Because the Config tab requires that a specific design is running in the FPGA, writing
a 0 to SRST or changing the PSO value can cause the Board Test System to stop
running.

JTAG Chain

The JTAG chain control shows all the devices currently in the JTAG chain. The
Stratix IV E device is always the first device in the chain.

Installing the shunt jumper on jumper J10 includes the MAX II device in the JTAG
chain.

SOPC Builder Memory Map

The SOPC Builder memory map control shows the memory map of the FPGA
design’s SOPC Builder system.