Altera Designing With Low-Level Primitives - Manual (Page 52)

2–30 Altera Corporation
Designing with Low-Level Primitives User Guide April 2007
Primitives
The CARRY primitive is supported for backward-compatibility with old
designs; new designs should use the CARRY_SUM primitive. If you use
either primitive incorrectly, it is ignored, and the Quartus II software
issues a warning message in the Message processor.
Example 2–22 shows a Verilog HDL example of a CARRY_SUM primitive
instantiation.
Example 2–22. CARRY_SUM Primitive Instantiation, Verilog HDL
carry_sum <instance_name> (.sin(>), .cin(<input_wire2>),
.sout(<output_wire1>), .cout(<output_wire2>);
Example 2–23 shows a VHDL component declaration for a CARRY_SUM
primitive instantiation.
Example 2–23. CARRY_SUM Primitive Instantiation, VHDL Component Declaration
COMPONENT CARRY_SUM
PORT (sin, cin : IN STD_LOGIC;
sout, cout : OUT STD_LOGIC);
END COMPONENT;
CASCADE
The CASCADE buffer enables the cascade-out function from one logic cell
and acts as a cascade-in to another logic cell. The cascade-in function
allows a cascade, which is a fast output located on each combinational
logic cell, to be OR’d or AND’d with the output of an adjacent
combinational logic cell within the FPGA.
The CASCADE primitive is only supported with the FLEX 10K ® and
APEX™ family of FPGAs. If you attempt to use the CASCADE primitive
with a non-supported FPGA family, an error message occurs.
When you use a CASCADE primitive, you must observe the following
rules:
■ A CASCADE primitive can feed or be fed only by a single gate, which
must be an AND or an OR gate.
■ An inverted OR gate is treated as an AND gate and vice-versa.
Logical equivalents of AND gates are BAND, BNAND, and NOR.
Logical equivalents of OR gates are BOR, BNOR, and NAND.
■ Two CASCADE primitives cannot feed the same gate.
■ A CASCADE primitive cannot feed an XOR gate.