Altera Designing With Low-Level Primitives - Manual (Page 10)

1–4 Altera Corporation
Designing with Low-Level Primitives User Guide April 2007
Low-Level Primitive Examples
Figure 1–1. Logic Merged During the Process
By strategically placing the LCELLs, you can control how the Quartus II
synthesis engine splits your design into logic cells. This typically causes
your design to use more logic resources, so this primitive should be used
with care. In the following example, and the resulting view from the
Quartus II Technology Map Viewer (
Figure 1–2 ), three LCELL primitive
instantiations are introduced between the combinational logic. Note that
“LCELL” is also the name that the Technology Map Viewer gives to the
logic cells in some device families, as shown in the figure.