Altera Designing With Low-Level Primitives - Manual (Page 34)

2–12 Altera Corporation
Designing with Low-Level Primitives User Guide April 2007
Primitives
Example 2–9 shows a VHDL component instantiation example of an
ALT_INBUF_DIFF primitive.
Example 2–9. ALT_INBUF_DIFF Primitive, VHDL Component Instantiation
library ieee;
use ieee.std_logic_1164.all;
library altera;
use altera.altera_primitives_components.all;
entity test_inbuf is
port (
in1,in2,in3 : in std_logic;
out1 : out std_logic
);
end test_inbuf;
architecture test of test_inbuf is
signal tmp1: std_logic;
begin
inst : ALT_INBUF_DIFF
generic map (
IO_STANDARD => "LVDS",7
LOCATION => "IOBANK_3"
)
port map (
i => in1,
ibar => in2,
o => tmp1
) ;
out1 <= in3 and tmp1;
end test;