Carry and carry_sum – Altera Designing With Low-Level Primitives User Manual
Page 51
Altera Corporation
2–29
April 2007
Designing with Low-Level Primitives User Guide
Primitive Reference
shows a VHDL component declaration for a
DFF primitive
instantiation.
Example 2–21. DFF Primitive Instantiation, VHDL
COMPONENT DFFEAS
PORT (d : IN STD_LOGIC;
clk : IN STD_LOGIC;
clrn : IN STD_LOGIC;
prn : IN STD_LOGIC;
ena : IN STD_LOGIC;
asdata : IN STD_LOGIC;
aload : IN STD_LOGIC;
sclr : IN STD_LOGIC;
sload : IN STD_LOGIC;
q : OUT STD_LOGIC );
END COMPONENT;
CARRY and CARRY_SUM
The
CARRY_SUM primitive is a two-input, two-output primitive that
designates the carry-out and sum-out logic for a function. The
cout port
of the primitive acts as the carry-in for the next element of the carry chain.
This
CARRY function also implements fast carry-chain logic for functions
such as adders and counters. The
CARRY_SUM primitive does not
generate the carry or sum logic, but indicates to the compiler that the
wires connected to it should be placed on the fast carry-chain logic wires
if possible.
When you use a
CARRY_SUM primitive, you must observe the following
rules:
■
The
cout port of the CARRY_SUM primitive can feed one or two
cones of logic. If the
CARRY_SUM primitive feeds two cones of logic,
one and only one of the cones of logic must be buffered by another
CARRY_SUM primitive. In this case, both cones of logic are
implemented in the same logic cell. You must follow this rule to tie
down the sum and carry-out functions for the first stage of an adder
or counter.
■
A cone of logic that feeds the
cin port of a CARRY_SUM primitive can
have up to two inputs. A third input is allowed only if it is a
CARRY_SUM input or a q feedback from the register.
■
The
cout port of the CARRY_SUM primitive cannot feed an output
pin.
■
The
cin port of the CARRY_SUM primitive cannot be fed by an input
pin.
■
The
cout port of two different CARRY_SUM primitives cannot feed
the same gate.