Altera Designing With Low-Level Primitives - Manual (Page 43)

Altera Corporation 2–21
April 2007 Designing with Low-Level Primitives User Guide
Primitive Reference
Example 2–13. ALT_IOBUF_DIFF Primitive, VHDL Component Instantiation
library ieee;
use ieee.std_logic_1164.all;
library altera;
use altera.altera_primitives_components.all;
entity test_iobuf is
port (
in1, in2, oe : in std_logic;
bidir, bidir_n : inout std_logic;
out : out std_logic
);
end test_iobuf;
architecture test of test_iobuf is
signal tmp1: std_logic;
tmp1 <= in1 and in2;
begin
inst : ALT_IOBUF_DIFF
generic map (
IO_STANDARD => "LVDS",
LOCATION=> "IOBANK_3"
)
port map (
i => tmp1,
oe => oe,
o => out,
io => bidir,
iobar => bidir_n
) ;
end test;