Altera Cyclone V GT FPGA - Manual (Page 42)

6–20 Chapter 6: Board Test System
The Clock Control
Cyclone V GT FPGA Development Kit September 2014 Altera Corporation
User Guide
■ The Si570 and Si571 programmable oscillators are connected to the MAX V device
through a 2-wire serial bus.
Figure 6–11 shows the Clock Control X4 tab (Si570), which has the same controls as
the X3 (Si571) tab.
Clock Control Controls
The following sections describe the Clock Control controls.
Serial Port Registers
This group shows the current values from the Si570 (X4 tab) and Si571 (X3 tab)
registers.
f
For more information about the registers, refer to the Si570/Si571 data sheet available
on the Silicon Labs website (
www.silabs.com ).
fXTAL
Displays the calculated internal fixed-frequency crystal, based on the serial port
register values.
f
For more information about the f
XTAL
value and how it is calculated, refer to the
Si570/Si571 data sheet available on the Silicon Labs website ( www.silabs.com ).
Figure 6–11. The Clock Control - X4 Tab