Start, Stop, Performance indicators – Altera Cyclone V GT FPGA User Manual
Page 33: Start –11 stop –11 performance indicators –11
Chapter 6: Board Test System
6–11
Using the Board Test System
September 2014
Altera Corporation
Cyclone V GT FPGA Development Kit
User Guide
shows the DDR3x64 tab. Except for the tab name and photograph, this tab
is identical to the DDR3x40 tab.
The following sections describe the controls on the DDR3x40 and DDR3x64 tabs.
Start
Initiates DDR3 memory transaction performance analysis.
Stop
Terminates the transaction performance analysis.
Performance Indicators
Display current transaction performance analysis information collected since you last
clicked Start:
■
Write
, Read, and Total performance bars—Show the percentage of the maximum
theoretical data rate that the requested transactions are able to achieve.
Figure 6–7. The DDR3x64 Tab
See also other documents in the category Altera Measuring instruments:
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- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
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- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
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- Cyclone III FPGA Starter Kit (36 pages)
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- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)