Preparing to run the board test system, Running the board test system – Altera Cyclone V GT FPGA User Manual
Page 24
6–2
Chapter 6: Board Test System
Preparing to Run the Board Test System
Cyclone V GT FPGA Development Kit
September 2014
Altera Corporation
User Guide
1
The Board Test System and Power Monitor share the JTAG bus with other
applications like the Nios II debugger and the SignalTap
®
II Embedded Logic
Analyzer. Because the Quartus II programmer uses most of the bandwidth of the
JTAG bus, other applications using the JTAG bus might time out. Be sure to close the
other applications before attempting to reconfigure the FPGA using the Quartus II
Programmer.
Preparing to Run the Board Test System
With the power to the board off, do the following:
1. Connect the USB cable to the board.
2. Ensure that the Ethernet patch cord is plugged into the RJ45 connector.
3. Ensure that the development board switches and jumpers are set to the default
“Factory Default Switch and Jumper Settings”
4. Set the SW4.3 DIP switch to the FACT OFF (logic 1) position.
5. Turn on the power to the board. The board loads the design stored in the user
hardware 1
portion of flash memory into the FPGA. The design loads the System
Info
, GPIO, Flash tabs and related tests under the following conditions:
■
Your board is still in the factory configuration.
■
You have downloaded a newer version of the Board Test System to flash
memory through the Board Update Portal.
c
To ensure operating stability, keep the USB cable connected and the board
powered on when running the demonstration application. The application
cannot run correctly unless the USB cable is attached and the board is on.
Running the Board Test System
To run the Board Test System, make sure you have first installed the software. Follow
the steps in
“Installing the Development Kit” on page 3–2
You can start the Board Test System with the following:
■
The BoardTestSystem.exe application that resides in
directory.
■
The Windows Start menu: All Programs > Altera > Cyclone V GT FPGA
Development Kit
<version> > Board Test System.
Once the Board Test System application GUI appears, it displays the application tab
that corresponds to the design running in the FPGA. The board’s flash memory ships
preconfigured with the design that corresponds to the System Info, GPIO, Flash tabs.