Altera Cyclone V GT FPGA - Manual (Page 38)

6–16 Chapter 6: Board Test System
Using the Board Test System
Cyclone V GT FPGA Development Kit September 2014 Altera Corporation
User Guide
The following sections describe the controls on the HSMB tab.
Start, Stop
The Start and Stop controls at the bottom-right of this tab allow you to start and stop
testing for both ports.
XCRV and CMOS
The XCRV and CMOS groups display the following status information during the
loopback test:
Data rate —Displays the current data rate in megabytes per second (MBps).
Freq —Displays the data rate frequency in MHz which is equivalent to MBps.
Bits —Displays the number of bits transmitted since clicking Start.
Inserted errors —Displays the number of errors inserted by clicking Insert Error
button.
Detected errors —Displays the number of bit errors detected by the error checking
circuitry.
BER —Displays the bit error rate of the interface.
Status
■ PLL lock —Displays Yes if the PLL is locked.
■ Pattern Sync —Displays Yes if the receiver has detected the input data pattern.
Start— Starts the PRBS data test and begins to monitor and update screen with live
test results.
Stop —Stops the PRBS data test.
Insert Error —Inserts an error into a data stream that is detected by the receiver when
in loopback mode. With the Insert Error, there are differences among the three ports:
■ XCVR—Inserts 4 errors at 1 click.
■ CMOS—Inserts 1 error at 1 click.
Clear —Clears the Detected errors counter.