The hsmb tab, The hsmb tab –15 – Altera Cyclone V GT FPGA User Manual
Page 37
Chapter 6: Board Test System
6–15
Using the Board Test System
September 2014
Altera Corporation
Cyclone V GT FPGA Development Kit
User Guide
Data Type
—Specifies the type of data contained in the transactions. The following
data types are available for analysis:
■
PRBS7
—Pseudo-random 7-bit sequences
■
PRBS15
—Pseudo-random 15-bit sequences
■
PRBS23
—Pseudo-random 23-bit sequences
■
PRBS31
—Pseudo-random 31-bit sequences
■
HF
—Highest frequency divide-by-4 data pattern 10101010
■
LF
—Lowest frequency divide-by-4 data pattern 11110000
The HSMB Tab
The HSMB tab (
) allows you to perform loopback tests on the HSMB
transceiver (XCVR) and HSMB CMOS ports
.
HSMB stands for high-speed mezzanine
card for Port B.
1
You must have the loopback HSMB installed on the HSMC Port B connector for this
test to work correctly.
Figure 6–9. The HSMB Tab
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)