Altera Cyclone V GT FPGA - Manual (Page 41)

Chapter 6: Board Test System 6–19
The Clock Control
September 2014 Altera Corporation Cyclone V GT FPGA Development Kit
User Guide
■ Power rail —Indicates the currently-selected power rail. After selecting the desired
rail, click Reset to refresh the screen with updated board readings.
f A table with the power rail information is available in the Cyclone V GT
FPGA Development Board Reference Manual .
Power Information
Displays current, maximum, and minimum numerical power readings in mA.
Power Graph
Displays the mA power consumption of your board over time. The green line
indicates the current value. The red line indicates the maximum value read since the
last reset. The yellow line indicates the minimum value read since the last reset.
Graph Settings
The following controls allow you to define the look and feel of the power graph:
■ Scale select —Specifies the amount to scale the power graph. Select a smaller
number to zoom in to see finer detail. Select a larger number to zoom out to see the
entire range of recorded values.
■ Update speed —Specifies how often to refresh the graph.
Reset
Clears the graph, resets the minimum and maximum values, and restarts the Power
Monitor.
The Clock Control
You can start the application with the following:
■ The ClockControl.exe application that resides in the dir>\kits\cycloneVGT_5cgtfd9ef35_fpga\examples\board_test_system
directory.
■ The Windows Start menu: All Programs > Altera > Cyclone V GT FPGA
Development Kit
<version>.
Clock Control Features
The Clock Control application sets the Si570 and Si571 programmable oscillators to
any frequency between 10 MHz and 810 MHz.
■ The Si570 (not the Si571) oscillator drives a 1-to-6 buffer that drives a copy of the
clock to the following areas of the FPGA:
■ Top, bottom, and right edges
■ REFCLK0 and REFCLK3
■ The 6th clock outputs to SMAs J4 and J7 on the board.
■ The Clock Control communicates with the MAX V device on the board through
the JTAG bus.