Altera Cyclone V GT FPGA User Manual
Page 16
4–4
Chapter 4: Development Board Setup
Factory Default Switch and Jumper Settings
Cyclone V GT FPGA Development Kit
September 2014
Altera Corporation
User Guide
2. Set the DIP switch bank (SW4) to match
and
.
3. Set the DIP switch bank (SW5) to match
and
.
3
HSMB_EN
Switch 3 has the following options:
■
ON (logical 0) = HCMC Port B not in JTAG chain.
■
OFF (logical 1) = Include HCMC Port B in the JTAG
chain.
ON
4
HSMA_EN
Switch 4 has the following options:
■
ON (logical 0) = HCMC Port A not in JTAG chain.
■
OFF (logical 1) = Include HCMC Port A in the JTAG
chain.
ON
Table 4–2. SW4 DIP Switch Settings
Switch
Board
Label
Function
Default
Position
1
CLKSEL
Switch 1 has the following options:
■
ON (logical 0) = SMA input clock select.
■
OFF (logical 1) = Programmable oscillator
clock select.
OFF
2
CLKEN
—
ON
3
FACT
Switch 3 has the following options:
■
ON (logical 0) = Load the factory design from
flash at power up.
■
OFF (logical 1) = Load the user design from
flash at power up.
ON
4
MODE
Switch 4 is an optional user switch setting. It is
not currently defined in the MAX 5 system
controller.
ON
Table 4–3. SW5 DIP Switch Settings (Part 1 of 2)
Switch
Board
Label
Function
Default
Position
1
MSEL1
Switch 1 has the following options:
■
When ON, a logic 0 is selected.
■
When OFF, a logic 1 is selected.
ON
2
MSEL2
Switch 2 has the following options:
■
When ON, a logic 0 is selected.
■
When OFF, a logic 1 is selected.
OFF
Table 4–1. SW3 DIP Switch Settings (Part 2 of 2)
Switch
Board
Label
Function
Default
Position