Altera Audio Video Development Kit, Stratix IV GX Edition User Manual
Page 19
![background image](https://www.manualsdir.com/files/763690/content/doc019.png)
Chapter 4: Development Board Setup
4–3
Factory Default Switch Settings
© November 2009 Altera Corporation
Audio Video Development Kit, Stratix IV GX Edition User Guide
To restore the switches to their factory default settings, perform the following steps:
1. Set the rotary switch (SW2) to the 0 position, as shown in
.
2. Set DIP switch bank (SW3) to match
3. Set DIP switch bank (SW4) to match
Figure 4–2. Switch Locations and Default Settings on the Development Board Bottom
Table 4–1. SW3 Dip Switch Settings
Switch
Position
1
Off
2
Off
3
Off
4
Off
5
Off
6
Off
7
Off
8
Off
Table 4–2. SW4SW4 Dip Switch Settings (Part 1 of 2)
Switch
Position
1
Off
2
Off
3
On
4
Off
5
On
6
On
4
3
2
1
SW4
8
7
6
5
4
3
2
1
ON
ON = 0
OFF = 1
SW6
ON
4
3
2
1
SW5
ON
PCIe
JTAG
Board
Settings
ON = 0
OFF = 1
See also other documents in the category Altera Measuring instruments:
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)