Altera ASI MegaCore Function - Manual (Page 6)

1–2 Chapter 1: About This MegaCore Function
Features
Asynchronous Serial Interface (ASI) MegaCore Function User Guide January 2014 Altera Corporation
Features
This section summarizes the features of the ASI MegaCore function.
■ IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators
■ Easy-to-use MegaWizard TM interface
■ Support for OpenCore Plus evaluation
General Description
The ASI MegaCore function demonstrates how to transmit or receive packets over an
ASI. The ASI MegaCore function works with 270 megabits per second (Mbps) DVB-
ASI, as defined by the DVB-ASI specification EN 50083-9 from CENELEC / December
2002 “Cable networks for television signals, sound signals and interactive services. Part 9:
Interfaces for CATV/SMATV head-ends and similar professional equipment for DVB/MPEG2
transport streams”.
f
For information on ASI MegaCore function demonstration on the Altera Cyclone
Video Demonstration Board, refer to the
Cyclone Video Demonstration Board Data Sheet .
MegaCore Verification
The ASI MegaCore verification involves the testing of the DVB-ASI specification
EN 50083-9 from CENELEC / December 2002 “Cable networks for television signals, sound
signals and interactive services. Part 9: Interfaces for CATV/SMATV head-ends and similar
professional equipment for DVB/MPEG2 transport streams”.
Cyclone III LS (1) Preliminary
Cyclone IV GX (2) Preliminary
Cyclone IV E (1.2V) Preliminary
Stratix ® III (1) Final
Stratix IV (3) Final
Other device families No support
Notes to Table 1–2 :
(1) The Cyclone series of devices and the Stratix III devices only support soft SERDES.
(2) Cyclone IV GX support includes all density in the device family except the EP4CGX15, EP4CGX22, and EP4CGX30
(excluding the EP4CGX30F484 pin package) devices.
(3) Stratix IV GT only supports soft logic mode.
Table 1–2. Device Family Support (Part 2 of 2)
Device Family Support