Altera ASI MegaCore Function User Manual
Page 25
A–4
Appendix A: Constraints
Minimize Timing Skew
Asynchronous Serial Interface (ASI) MegaCore Function User Guide
January 2014
Altera Corporation
The following code is an example of a constraint, which you can set using the
Quartus II Assignment Editor:
set_location_assignment PIN_99 -to asi_rx0
set_location_assignment LC_X32_Y17_N0 -to
"asi_rx:u_rx0|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi
rx_gen.u_rx|serdes_s2p:u_s2p|sample_a[0]"
set_location_assignment LC_X33_Y17_N0 -to
"asi_rx:u_rx0|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi
rx_gen.u_rx|serdes_s2p:u_s2p|sample_b[0]"
set_location_assignment LC_X32_Y17_N1 -to
"asi_rx:u_rx0|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi
rx_gen.u_rx|serdes_s2p:u_s2p|sample_c[0]"
set_location_assignment LC_X33_Y17_N1 -to
"asi_rx:u_rx0|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi
rx_gen.u_rx|serdes_s2p:u_s2p|sample_d[0]"
Figure A–1
shows the placement of these registers in the Quartus II chip planner
floorplan.
Figure A–1. Register Placement
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)