Specify clocks that are exclusive or asynchronous, Minimize timing skew – Altera ASI MegaCore Function User Manual

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Appendix A: Constraints

A–3

Minimize Timing Skew

January 2014

Altera Corporation

Asynchronous Serial Interface (ASI) MegaCore Function User Guide

Specify Clocks that are Exclusive or Asynchronous

The ASI MegaCore function may show timing violations in slower speed grade
devices. These paths are not required to have fast timing, so you can use the following
constraints to remove these timing paths. The command set_clock_groups can be
used.

For ASI RX (soft transceiver), set the following false paths:

set_false_path from
{asi_megacore_top:asi_megacore_top_inst|asi_receive:asi_rx_gen.u_rx
|serdes_s2p:u_s2p|sample_0[*]} to
{asi_megacore_top:asi_megacore_top_inst|asi_receive:asi_rx_gen.u_rx
|serdes_s2p:u_s2p|dout[*]}

set_false_path from
{asi_megacore_top:asi_megacore_top_inst|asi_receive:asi_rx_gen.u_rx
|serdes_s2p:u_s2p|sample_1[*]} to
{asi_megacore_top:asi_megacore_top_inst|asi_receive:asi_rx_gen.u_rx
|serdes_s2p:u_s2p|dout[*]}

set_false_path from
{asi_megacore_top:asi_megacore_top_inst|asi_receive:asi_rx_gen.u_rx
|serdes_s2p:u_s2p|start_read} to
{asi_megacore_top:asi_megacore_top_inst|asi_receive:asi_rx_gen.u_rx
|serdes_s2p:u_s2p|dout[*]}

The following SDC commands are applicable for ASI RX (soft transceiver) using
Stratix IV devices.

set_clock_groups -exclusive -group [get_clocks {tx_clk135}] -group
[get_clocks
{asi_megacore_top_inst|asi_tx_gen.u_tx|u_gxb4_tx.u_gxb|alt4gxb_comp
onent|auto_generated|transmit_pcs0|clkout}]

You must use the constraint entry dialog boxes for other device families.

Minimize Timing Skew

You should minimize the timing skew among the paths from I/O pins to the four
sampling registers (sample_a[0], sample_b[0], sample_c[0], and sample_d[0]). To
minimize the timing skew, manually place the sampling registers close to each other
and to the serial input pin. Because these four registers are using four different clock
domains, place two of the four registers in one LAB and the other two in another LAB.
Furthermore, place the 2 chosen LABs within the same row whatever the placement
of the serial input. Finally, do not place the four sampling registers at the immediate
rows or columns next to the I/O, but the second one next to the I/O bank. This
location is because inter-LAB interconnects between I/O banks and their immediate
rows or columns are much faster than core interconnect.

Optimizing beneficial skew may add unwanted delay to the sampling clocks and
cause performance degradation or failure. To avoid this unwanted delay for all
sampling registers, in the Fitter settings, select Off for Enable Beneficial Skew
Optimization