Parameter settings, Chapter 3. parameter settings – Altera ASI MegaCore Function User Manual
Page 15
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January 2014
Altera Corporation
Asynchronous Serial Interface (ASI) MegaCore Function User Guide
3. Parameter Settings
Table 3–1
summarizes the parameters.
1
You can change the page that the MegaWizard Plug-In Manager displays by clicking
Next
or Back at the bottom of the dialog box. You can move directly to a named page
by clicking the Parameter Settings, EDA, or Summary tab.
Table 3–1. Parameters
Parameter
Range
Description
Currently selected device
family
—
Shows the device family that you chose in your
Quartus II project.
Interface type
Receiver or transmitter
Select a receiver or transmitter for you custom
variation.
Transceiver and protocol
Generate transceiver and protocol
blocks, or generate transceiver only,
or generate protocol blocks only
Select the blocks for your custom variation.
Use soft logic for
transceiver
On or off
For Stratix IV GX devices, specify soft logic for the
transceiver. When you turn on Use soft logic for
transceiver, the transceiver is implemented in the
device’s logic, otherwise the design uses a
Stratix IV GX transceiver.
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)