Altera Nios II Embedded Evaluation Kit Cyclone III Edition - Manual (Page 51)

Altera Corporation Development Board Version 1.0. A–1
July 2010 Preliminary
Appendix A. Video Pipeline
Data Flow
Introduction The video display subsystem embodied in the Nios II Embedded
Evaluation Kit designs was intentionally-designed to be modular &
flexible to make customizing a snap. The design style used for the video
pipeline highlights the use of several simple microcores which can be
configured or customized for other video applications.
The video subsystem consists of these operational components, in
roughly-logical order:
■ A frame-buffer (which happens to reside in DDR SDRAM memory)
■ A memory-to-stream DMA controller, which reads memory 64 bits
at a time and produces a stream of 64-bit data values.
■ A width (data format adapter) to break the 64-bit stream into
sequential 32-bit (pixel) values.
■ A FIFO
■ A Pixel Format Converter
■ Another Data Format Adapter, to produce a stream of 8-bit values.
■ A sync-generator (which you could think of as an LCD-display PHY)
1 If you actually look at the design, there are several other Avalon
Streaming components in this flow. These have been omitted
from this discussion for clarity because they are not operational.
They are just timing-adapters which allow the operational
pieces to fit together properly.
Starting from the end of the chain: The sync-generator just takes a stream
of 8-bit-wide data values on its streaming input. Three consecutive 8-bit
values make a single color pixel (R, G, B, R, G, B…) An start of packet
(SOP)-pulse marks the start of each frame. The sync-generator drives
external pins so that the pixel-stream appears on the display.
The DMA controller fetches pixel-data from the in-memory frame-buffer
and drives it in row-major (raster) order on its streaming output-port and,
through the video-subsystem pipeline, to the sync-generator termination.
The system has a FIFO because all systems like this always have FIFOs.
It’s there to “take up the slack” and keep the display fed even when the
DDR SDRAM memory is unavailable (due to contention, refresh, etc.).