Nios ii 3c25 video processor system – Altera Nios II Embedded Evaluation Kit Cyclone III Edition User Manual
Page 28
Altera Corporation
Development Board Version 1.0.
3–4
July 2010
Nios II Embedded Evaluation Kit, Cyclone III Edition
Nios II Processor Systems
Nios II 3C25 Video Processor System
Location
You can locate the Nios II 3C25 Video Processor System in the <install
dir>/examples/video folder.
Description
Video, Ethernet and SD Card controller based processor system for LCD
Color touch panel control, in-system update using SD Card, remote
system update using Ethernet
IP licenses required to ship design
■
SD/MMC SPI Core IP (with FAT file system) from El Camino
■
Triple Speed Ethernet-MAC Core license from Altera
■
Nios II IP evaluation license with Nios II EDS, shipping license from
Altera
■
DDR SDRAM memory controller core shipping license from Altera
(comes free with Quartus II Subscription edition)
About the Nios II 3C25 Video Processor
CPU Platform
The CPU platform for the Nios II Standard System consists of
■
Nios II/f cpu core
■
JTAG Debug Port
■
32KB Instruction Cache
■
32KB Data Cache
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)