Development board setup, Features, Chapter 2. development board setup – Altera Nios II Embedded Evaluation Kit Cyclone III Edition User Manual
Page 21
Altera Corporation
Development Board Version 1.0.
2–1
July 2010
Preliminary
2. Development Board Setup
Features
The Nios II Embedded Evaluation Kit features:
■
Cyclone III Starter Board
●
Cyclone III EP3C25F324 FPGA
●
Configuration
•
Embedded USB-Blaster™ circuitry (includes an Altera
EPM3128A CPLD) allowing download of FPGA
configuration files via the users USB port
●
Power and analog devices from Linear Technology
●
Memory
•
256-Mbit DDR SDRAM
•
1-Mbyte Synchronous SRAM
•
16-Mbytes Intel P30/P33 flash
●
Clocking
•
50-MHz on-board oscillator
●
Switches and indicators
•
Six push buttons total, 4 user controlled
•
Four user-controlled LEDs
■
LCD Daughtercard
●
LCD Touch-screen Display
•
800 X 480 pixel size
●
10-bit VGA DAC
●
Video Decoder
●
24-bit Audio Codec
●
RS232 transceiver
●
SD Flash
●
10/100 Mbps Ethernet Controller (PHY)
●
Connectors
•
VGA Output
•
Composite Video in
•
Serial connector (RS-232 DB9 port)
•
PS/2
•
Ethernet Connector (RJ 45)
•
SD Card Socket
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)