ADLINK PCIe-7350 - Manual (Page 61)

Function Block and Operation Theory 51
The timing diagram of DO DMA in burst handshaking mode is
shown as below:
Figure 3-21: DO Burst Handshaking Timing Diagram
DO
DO Data
Exported DO Sampled Clock
(falling edge)
DO Sampled Clock
DO -REQ
(Active High)
DO -ACK
(Active High)
D1 D2 D3 D4 D5 D6 D7 D8
Up to 4 samples are allowed to
transfer after de-assertion of DO-ACK
External device is ready
to receive DO data
PCIe-7350 is ready to send DO data