ADLINK PCIe-7350 - Manual (Page 38)

28 Function Block and Operation Theory
Value
Revolution 16 steps (1 step = 22.5°)
Supported
Frequency Range
2MHz ~ 50MHz
Supported CLK
User can shift the clock phase ofthe following clock:
External DI sample clock (from SMB CLK IN or AFI7)
External DO sample clock (from SMB CLK IN or AFI6)
Exported DI sample clock (from SMB CLK IN or AFI7)
Exported DO sample clock (from SMB CLK IN or AFI6)
Table 3-3: Phase Shift Configuration of PCIe-7350