ADLINK PCIe-7350 - Manual (Page 47)

Function Block and Operation Theory 37
The timing diagram of DI DMA in continuous mode is shown as
below:
Figure 3-11: DI Timing Diagram
Note: In the continuous mode of DI pattern acquisition, the input
data will be stored in the DI FIFO of the PCIe-7350. The data
then transfer to system memory by bus mastering DMA if
PCIe bus is available. If the speed of translation from exter-
nal device to the DI FIFO on board is higher than that from
DI FIFO to system memory or the PCIe bus is busy for a long
time, the DI FIFO become full and the DI pattern acquisition
controller will stop to write data into DI FIFO until the DI FIFO
is not full. So the data will be lost when the DI FIFO is full.
DO D1 D2 D3 D4 D5 D6
DI Sampled Clock
Start Trigger
DI Data
Read data into DI FIFO Wait for
start trigger
t
H
t
SU
t
H
t
SU
t
H
t
SU
= Maximum required setup time
= Maximum required hold time