Digilent 6015-410-001P-KIT User Manual
Digilent Hardware
Table of contents
Document Outline
- Table of Contents
- Overview
- 1 FPGA Configuration
- 2 Power Supplies
- 3 Oscillators and Clocks
- 4 FPGA Memory
- 5 DDR3 Memory
- 6 QDRII+ Memory
- 7 BPI Flash Memory
- 8 SD Card
- 9 PCIe Interface
- 10 Ethernet PHYs
- 11 PIC Subsystem
- 12 On-Board I/O
- 13 PMOD Expansion Connectors
- 14 FMC Expansion Connector
- Appendix A: Manufacturing Test
- Appendix B: FPGA Pin Constraints
- LOC = H2;
- NET pcie-rx0_p
- LOC = J4;
- NET pcie-tx0_p
- LOC = H1;
- NET pcie-rx0_n
- LOC = J3;
- NET pcie-tx0_n
- LOC = K2;
- NET pcie-rx1_p
- LOC = L4;
- NET pcie-tx1_p
- LOC = K1;
- NET pcie-rx1_n
- LOC = L3;
- NET pcie-tx1_n
- LOC = M2;
- NET pcie-rx2_p
- LOC = N4;
- NET pcie-tx2_p
- LOC = M1;
- NET pcie-rx2_n
- LOC = N3;
- NET pcie-tx2_n
- LOC = M2;
- NET pcie-rx3_p
- LOC = N4;
- NET pcie-tx3_p
- LOC = M1;
- NET pcie-rx3_n
- LOC = N3;
- NET pcie-tx3_n
- LOC = H6;
- NET pcie-clk_p
- LOC = H5;
- NET pcie-clk_n
- NODELAY;
- PULLUP
- IOSTANDARD = LVCMOS33
- LOC = L17
- NET pcie-perstn
- IOSTANDARD = LVCMOS33;
- LOC = K18
- NET pcie-wake
- IOSTANDARD = LVCMOS18;
- LOC = AA7
- NET pcie-prsnt