Digilent 6015-410-001P-KIT - Manual (Page 13)

NetFPGA-1G-CML™ Board Reference Manual
Appendix B: FPGA Pin Constraints
The following list provides LOC and IOSTANDARD constraints for the main peripheral pins connected to the FPGA.
This information can be used in a design UCF file with Xilinx ISE Design Suite, a design XDC file with Xilinx Vivado
Design Suite, or with various interface generators included with Xilinx Coregen and MIG. Please see the Xilinx
Constraints Guide (UG625) for ISE Design Suite based designs and Xilinx Vivado Design Suite User Guide: Using
Constraints (UG903) for Vivado based designs.
Depending upon the design suite selected, this information can be expressed in either a UCF file or an XDC file as
follows:
UCF format used with ISE Design Suite
NET LOC= | IOSTANDARD=;
XDC format used with Vivado Design Suite
set_property IOSTANDARD [get_ports { }]
set_property LOC [get_ports ]
The information is presented in UCF format to express a clear association between the pin and the desired IO
standard for the NetFPGA-1G, although it can be readily translated into the XDC format. LOC information is
provided here for all pins. IOSTANDARD information is provided for SelectIO pins. Other useful properties are
suggested where appropriate.
System Clock and Reset
Port Name IO Location IO Standard Type
NET reset LOC = AA8
IOSTANDARD=LVCMOS18; # RESET button
(BTN4)
NET system_clk_p LOC = AA3 IOSTANDARD=LVDS;
NET system_clk_n LOC = AA2 IOSTANDARD=LVDS;
DDR3 SDRAM
Port Name IO Location IO Standard Type
NET ddr3_dq[0] LOC = AE5 IOSTANDARD = SSTL15_T_DCI;
NET ddr3_dq[1] LOC = AE3 IOSTANDARD = SSTL15_T_DCI;
NET ddr3_dq[2] LOC = AD4 IOSTANDARD = SSTL15_T_DCI;
NET ddr3_dq[3] LOC = AF3 IOSTANDARD = SSTL15_T_DCI;
NET ddr3_dq[4] LOC = AE1 IOSTANDARD = SSTL15_T_DCI;
NET ddr3_dq[5] LOC = AF2 IOSTANDARD = SSTL15_T_DCI;
NET ddr3_dq[6] LOC = AD1 IOSTANDARD = SSTL15_T_DCI;
NET ddr3_dq[7] LOC = AE2 IOSTANDARD = SSTL15_T_DCI;
NET ddr3_addr[0] LOC = Y3 IOSTANDARD = SSTL15;
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