Digilent 410-182P-KIT - Manual (Page 9)

Nexys3 Reference Manual
Doc: 502-182 page 9 of 22
controller (similar to any SRAM controller). When operated in synchronous mode, continuous
transfers of up to 80MHz are possible.
The parallel PCM device (Micron part number NP8P128A13T1760E) is organized as 8Mwords of
16bits each. It contains 128 individually erasable 64K-blocks, one of which is subdivided into four 16K
“parameter blocks” that can offer increased data protection. Normally, a device with a parameter block
at the high end of the address space is loaded (a “top parameter” block device). The parallel PCM
memory offers 115ns read cycle times, with 25ns page-mode reads within blocks. It has an internal
64-byte write buffer that can be written with 50ns cycle times, and the 64-byte buffer can be
transferred to the Flash array in 120us (typical). The parallel PCM device also contains an SPI port for
serial data transfer, but that function is not enabled on the Nexys3 board (the ADV and WAIT signals
are connected between the FPGA and PCM, but they serve no functions).
The Cellular RAM and parallel PCM share a common 16-bit data bus and 24-bit address bus. The
Cellular RAM is byte addressable using the upper-byte and lower-byte signals (MT-UB and MT-LB),
but the P8P PCM is configured for 16 byte operations only (it is not byte addressable). The output
enable (OE) and write enable (WE) signals are shared by both devices, but each device has individual
chip enable (CE) signals. Additionally, the Cellular RAM has clock (MT-CLK), wait (MT-WAIT),
address valid (MT-ADV) and control register enable (MT_CRE) signals available to the FPGA for use
with synchronous transfers, and the PCM device has Reset (RP#). With simple changes, the Nexys3
board can accommodate either the PCM device or the older “P33” Flash device. The signal names in
the Nexys3 schematic reference the P33 device; the P33 ADV and WAIT signals are not used in by
the PCM device.
The 16Mbyte serial PCM device (Micron part number NP5Q128A13ESFC0E) is also bit alterable
without requiring an erase cycle. It supports the legacy SPI protocol as well as the newer Quad I/O
and Dual I/O protocols, at bus speeds up to 50MHz.
FPGA configuration files can be written to both PCM devices, and mode settings are available to
cause the FPGA to automatically read a configuration from one of these devices at power on. A
Spartan-6 LX16 configuration file requires about 512Kbytes of memory, leaving about 97% of the
PCM devices available for user data.
Both PCM devices are loaded with configuration files at the factory. The SPI PCM device contains a
file that configures the FPGA to test the Nexys3 memory devices during manufacturing, and this file
isn’t needed after the board test is complete. The BPI PCM device contains a file that configures the
Nexys3 with a basic user demonstration program, and it can be used to verify board functions. This
same .bit file is available for download from the Digilent website. If Mode jumper J8 is set to BPI mode
and power is applied, the user demo configuration will be loaded. The demo drives a counter on the 7-
segment display, drives the user LEDs on and off when the user switches are toggled, turns off digits
on the 7-segment display when user buttons are pressed, and drives an image out the VGA port. A
USB mouse can be connected to J4 for a simple visual demonstration.
Please refer to the manufacturer’s data sheets and the reference designs posted on Digilent’s website
for more information about the memory devices.