Oscillators/clocks – Digilent 410-182P-KIT User Manual

Page 11

Nexys3 Reference Manual

Doc: 502-182

page 11 of 22

Ethernet PHY

The Nexys3 board includes an SMSC 10/100 Ethernet PHY (SMSC part number LAN8710) paired
with an RJ-45 Ethernet jack with integrated magnetics. EDK-based designs can access the PHY
using either the xps_ethernetlite IP core or the xps_ll_temac IP core. The Nexys3 Base System
Builder (BSB) support package automatically generates a test application for the Ethernet MAC; this
can be used as a reference for creating custom designs. ISE designs can use the IP Core Generator
wizard to create an Ethernet MAC controller IP core. The SMSC PHY uses the MII interface and
supports 10/100 Mb/s. At power-on reset, the PHY is set to the following defaults:



MII mode interface



100Base-TX with auto negotiation enabled, advertising half-duplex, with CRS active during

receive



PHY address = 000

Refer to the LAN8710A data sheet on the www.smsc.com website for further information.

Spartan 6

P3
P4

INT#/TXER/TXD4

RESET#
COL
CRS

RXDV
RXCLK

RXER/RXD4

TXCLK

TXEN

MDIO

25MHz
Crystal

MDC

CLK

RXD0

TXD0

SMSC LAN8710A

RJ-45 with

magnetics

Link/Status
LEDs (x2)

TXD1
TXD2
TXD3

RXD1
RXD2
RXD3

Oscillators/Clocks

The Nexys3 board includes a single 100MHz CMOS oscillator connected to pin V10 (V10 is the
GCLK0 input in bank 2). The input clock can drive any or all of the four clock management tiles in the