Kontron VMP1 - Manual (Page 28)

VMP1 Functional Description
ID 19972, Rev. 0101 Page 2 - 6 ® PEP Modular Computers GmbH
2.4 Main Features
The following descriptions provide an overview of the main features of the principal
functional blocks of the VMP1.
2.4.1 CPU
The VMP1 is based on the Motorola PowerPC processor MPC8240 which integrates a
large number of peripherals, such as a PCI interface, PCI arbiter, Interrupt Controller,
Memory Controller and multiple Timers. CPU speed is 250 MHz.
2.4.1.1 MPC8240 (Kahlua) Features
Important features of the MPC8240 implemented on the VMP1 are as follows:
Peripheral logic
Memory interface
• Programmable timing supporting either FPM DRAM, EDO DRAM or SDRAM
(The VMP1 uses SDRAM at 100 MHz)
• High bandwidth bus (64-bit data bus) to SDRAM
• 2 memory banks with up to 64 MB each (64 or 128 Mbit memory devices)
• Supports 32, 64, 96 and 128 MB SDRAM
• Contiguous memory mapping
• 8-bit ROM interface
• Write buffering for PCI and processor accesses
• Supports ECC
• SDRAM data path buffer
• Low voltage transistor-to-transistor logic (LVTTL)
• Port X: 8-bit general-purpose I/O port using ROM controller
interface with address strobe
32-bit PCI interface operating up to 33 MHz on the VMP1
• PCI Specification Revision 2.1 compatible
• PCI 5.0-V tolerance
• Support for PCI-locked accesses to memory
• Support for accesses to all PCI address spaces
• Selectable big- or little-endian operation
• Store gathering of processor-to-PCI write and PCI-to-memory write accesses
• Memory prefetching of PCI read accesses
• Selectable hardware-enforced coherency
• PCI bus arbitration unit (five request/grant pairs)