Achronix Speedster22i Clock and Reset Networks - Manual (Page 7)

UG027, May 21, 2014 7
Core Clock Network
This chapter focuses solely on the core clock network, illustrating the global and direct core
clock network hierarchies and providing a more in-depth look at the different components
that make up these networks.
Global and Direct Core Clock Network
Global Core Clock Network
The global core clock network is a balanced and low-skew H-tree that enables clock
distribution to all parts of the Speedster 22iHD FPGA fabric. Clock signals coming in from
the top and bottom CGs and SerDes blocks are routed through a clock hub and aggregated at
the center of the device. These are then provided to all clock regions (see section on Clock
Region for details) on both the west and east sides.
As shown in Table 1, a total of 48 global clock signals are generated in the clock hub. These
are then distributed to all clock regions. Every clock region supports up to a maximum of 16
clocks, and it is able to select, amongst other sources, any of the 48 available global clocks.
Figure 1 below provides a high level illustration of the routing and connection paths for the
H-tree global core clock network.