Achronix Speedster22i Clock and Reset Networks - Manual (Page 25)

UG027, May 21, 2014 25
and (b) even if it did the user wouldn’t be able to do anything to fix timing problems in the
I/O ring.
For resets going into the FPGA fabric, the guideline is to use logic in the fabric to ensure that
the resets can be synchronized to the particular clock domains. One way of doing this is
shown in Figure 15 below, whereby the logic enables going into reset asynchronously, but
coming out of it asynchronously.
D Q D Q
nclr nclr
To nclr ports of logic
receiving reset
Nrst
Clk
Figure 15: Reset Synchronization Logic
As far as the external reset sources arc concerned, all dedicated clock buffers can be used as
inputs to the Reset Input Block. Also, for IO banks bonded out on the East-North (EN), East-
South (ES), West-North (WN) or West-South (WS) sides of the device, a total of four IO pads
can be used as inputs to the Reset Input Block. The table below from the HD1000 52.5mm
package spreadsheet dumped out by ACE highlights all the RST pins that can be used. The 8
shown in the red rectangle are only available on the 52.5mm package and not on the 45mm
package since the IO banks on the East-South (ES) and West-North (WN) sides of the device
are not bonded out on the 45mm package.
Table 5: Snapshot of HD1000 52.5mm package spreadsheet to show resets
Port_Name DIFF-PAIR USE BANK PURPOSE CLK/RST USE
pad_en_byteio0_dq0 P G B50 USER RST
pad_en_byteio0_dq1 N G B50 USER RST
pad_en_byteio0_dq2 P G B50 USER RST
pad_en_byteio0_dq3 N G B50 USER RST
pad_es_byteio12_dq6 P G B32 USER RST
pad_es_byteio12_dq7 N G B32 USER RST
pad_es_byteio12_dq8 P G B32 USER RST
pad_es_byteio12_dq9 N G B32 USER RST
pad_wn_byteio0_dq0 P G B00 USER RST
pad_wn_byteio0_dq1 N G B00 USER RST
pad_wn_byteio0_dq2 P G B00 USER RST
pad_wn_byteio0_dq3 N G B00 USER RST
pad_ws_byteio12_dq6 P G B22 USER RST
pad_ws_byteio12_dq7 N G B22 USER RST
pad_ws_byteio12_dq8 P G B22 USER RST
pad_ws_byteio12_dq9 N G B22 USER RST
pad0_clk_bank_ne P C CB3 USER CLK RST
pad0_clk_bank_nw P C CB0 USER CLK RST