Achronix Speedster22i Clock and Reset Networks - Manual (Page 3)

UG027, May 21, 2014 3
Table of Contents
Copyright Info .................................................................................................... 2
Table of Contents .............................................................................................. 3
Introduction ....................................................................................................... 4
Clock and Reset Networks Overview ..................................................................................... 4
Clock Resource Counts ................................................................................................................. 4
Reset Resource Counts ................................................................................................................. 5
Clock Sources ........................................................................................................................ 6
Reset Sources ....................................................................................................................... 6
Core Clock Network .......................................................................................... 7
Global and Direct Core Clock Network .................................................................................. 7
Global Core Clock Network ............................................................................................................ 7
Direct Core Clock Network ............................................................................................................. 8
Core Clock Network Components ........................................................................................ 10
Clock Generator (CG) .................................................................................................................. 10
Phase Locked Loop (PLL) ............................................................................................................ 11
Clock Mux .................................................................................................................................... 14
Clock Hub .................................................................................................................................... 15
Clock Region ................................................................................................................................ 16
Clock Region Management Unit (CRMU) ..................................................................................... 17
Junctions .............................................................................................................................. 19
Data-to-Clock Junctions ............................................................................................................... 19
Clock-to-Data Junctions ............................................................................................................... 19
Byte-Lane Clocks ................................................................................................................. 20
Boundary Clock Network ................................................................................ 21
Clock Setting and Reporting .......................................................................... 23
Reset Network ................................................................................................. 24
Reset Sources and the Reset Input Block ........................................................................... 24
Reset Distribution ................................................................................................................. 26
Revision History .............................................................................................. 28